MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK  850 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK 0x00008000L
MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK  755 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_sh_mask.h #define MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK 0x8000
MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK  813 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK 0x8000
MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK  859 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK 0x8000
MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK  857 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_sh_mask.h #define MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK 0x8000