MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT  847 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT 0x0000000b
MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT  748 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_sh_mask.h #define MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT 0xb
MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT  806 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT 0xb
MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT  852 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT 0xb
MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT  850 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_sh_mask.h #define MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT 0xb