AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 13052 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4
AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 13058 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4
AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 13674 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4
AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 63695 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT                                                    0x4
AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 1430 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x00000004
AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 11948 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4
AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 46743 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT                                                    0x4
AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 60423 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT                                                    0x4
AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 49037 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT                                                    0x4