IH_RB_WPTR__OFFSET_MASK  758 drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_sh_mask.h #define IH_RB_WPTR__OFFSET_MASK 0x0003fffcL
IH_RB_WPTR__OFFSET_MASK   81 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define IH_RB_WPTR__OFFSET_MASK 0x3fffc
IH_RB_WPTR__OFFSET_MASK   81 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define IH_RB_WPTR__OFFSET_MASK 0x3fffc
IH_RB_WPTR__OFFSET_MASK   81 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define IH_RB_WPTR__OFFSET_MASK 0x3fffc
IH_RB_WPTR__OFFSET_MASK   83 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define IH_RB_WPTR__OFFSET_MASK 0x3fffc
IH_RB_WPTR__OFFSET_MASK  232 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_1_sh_mask.h #define IH_RB_WPTR__OFFSET_MASK                                                                               0x0003FFFCL
IH_RB_WPTR__OFFSET_MASK  230 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h #define IH_RB_WPTR__OFFSET_MASK                                                                               0x0003FFFCL
IH_RB_WPTR__OFFSET_MASK  232 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_sh_mask.h #define IH_RB_WPTR__OFFSET_MASK                                                                               0x0003FFFCL