IH_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK  750 drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_sh_mask.h #define IH_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003e00L
IH_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK   69 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define IH_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x3e00
IH_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK   69 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define IH_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x3e00
IH_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK   69 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define IH_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x3e00