IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT  164 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2
IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT  164 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2
IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT  170 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2
IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT  441 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_1_sh_mask.h #define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT                                                       0x2
IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT  435 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h #define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT                                                       0x2
IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT  441 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_sh_mask.h #define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT                                                       0x2