IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT  166 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT 0x3
IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT  166 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT 0x3
IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT  172 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT 0x3
IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT  442 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_1_sh_mask.h #define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT                                                          0x3
IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT  436 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h #define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT                                                          0x3
IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT  442 drivers/gpu/drm/amd/include/asic_reg/oss/osssys_5_0_0_sh_mask.h #define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT                                                          0x3