HDP_XDP_P2P_BAR5__FLUSH__SHIFT  486 drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h #define HDP_XDP_P2P_BAR5__FLUSH__SHIFT	0x10
HDP_XDP_P2P_BAR5__FLUSH__SHIFT  543 drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_5_0_0_sh_mask.h #define HDP_XDP_P2P_BAR5__FLUSH__SHIFT                                                                        0x10
HDP_XDP_P2P_BAR5__FLUSH__SHIFT  593 drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_sh_mask.h #define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x00000010
HDP_XDP_P2P_BAR5__FLUSH__SHIFT 2414 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10
HDP_XDP_P2P_BAR5__FLUSH__SHIFT 2482 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10
HDP_XDP_P2P_BAR5__FLUSH__SHIFT 3496 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10
HDP_XDP_P2P_BAR5__FLUSH__SHIFT 3598 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10