HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT  521 drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h #define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT	0x8
HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT  578 drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_5_0_0_sh_mask.h #define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT                                                                      0x8
HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT  405 drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_sh_mask.h #define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x00000008
HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 2442 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8
HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 2510 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8
HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 3524 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8
HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 3626 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8