HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL_MASK   36 drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h #define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL_MASK	0x00070000L
HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL_MASK   36 drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_5_0_0_sh_mask.h #define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL_MASK                                                                  0x00070000L