HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT  168 drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h #define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT	0x0
HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT  225 drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_5_0_0_sh_mask.h #define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT                                                                     0x0
HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT  255 drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_sh_mask.h #define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x00000000
HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 2148 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0
HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 2216 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0
HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 3222 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0
HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 3324 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0