HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT   69 drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT	0x13
HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT   89 drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_5_0_0_sh_mask.h #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT                                                        0x13
HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT  233 drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_sh_mask.h #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x00000013
HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 2006 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13
HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 2074 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13
HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 3076 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13
HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 3178 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13