ATTR05__ATTR_PAL__SHIFT 11272 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define ATTR05__ATTR_PAL__SHIFT 0x0
ATTR05__ATTR_PAL__SHIFT 11084 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define ATTR05__ATTR_PAL__SHIFT 0x0
ATTR05__ATTR_PAL__SHIFT 12338 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define ATTR05__ATTR_PAL__SHIFT 0x0
ATTR05__ATTR_PAL__SHIFT 64731 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define ATTR05__ATTR_PAL__SHIFT                                                                               0x0
ATTR05__ATTR_PAL__SHIFT  391 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h #define ATTR05__ATTR_PAL__SHIFT 0x00000000
ATTR05__ATTR_PAL__SHIFT 10888 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h #define ATTR05__ATTR_PAL__SHIFT 0x0
ATTR05__ATTR_PAL__SHIFT 46392 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h #define ATTR05__ATTR_PAL__SHIFT                                                                               0x0
ATTR05__ATTR_PAL__SHIFT 59996 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h #define ATTR05__ATTR_PAL__SHIFT                                                                               0x0
ATTR05__ATTR_PAL__SHIFT 48756 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h #define ATTR05__ATTR_PAL__SHIFT                                                                               0x0