GENS1__VGA_VSTATUS__SHIFT 11026 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define GENS1__VGA_VSTATUS__SHIFT 0x3
GENS1__VGA_VSTATUS__SHIFT 10838 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define GENS1__VGA_VSTATUS__SHIFT 0x3
GENS1__VGA_VSTATUS__SHIFT 12092 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define GENS1__VGA_VSTATUS__SHIFT 0x3
GENS1__VGA_VSTATUS__SHIFT 2186 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define GENS1__VGA_VSTATUS__SHIFT                                                                             0x3
GENS1__VGA_VSTATUS__SHIFT 7182 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h #define GENS1__VGA_VSTATUS__SHIFT 0x00000003
GENS1__VGA_VSTATUS__SHIFT 10642 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h #define GENS1__VGA_VSTATUS__SHIFT 0x3
GENS1__VGA_VSTATUS__SHIFT  825 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h #define GENS1__VGA_VSTATUS__SHIFT                                                                             0x3
GENS1__VGA_VSTATUS__SHIFT  236 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h #define GENS1__VGA_VSTATUS__SHIFT                                                                             0x3