GENMO_WT__VGA_HSYNC_POL__SHIFT 10998 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x6
GENMO_WT__VGA_HSYNC_POL__SHIFT 10810 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x6
GENMO_WT__VGA_HSYNC_POL__SHIFT 12064 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x6
GENMO_WT__VGA_HSYNC_POL__SHIFT 2207 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define GENMO_WT__VGA_HSYNC_POL__SHIFT                                                                        0x6
GENMO_WT__VGA_HSYNC_POL__SHIFT 7168 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h #define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x00000006
GENMO_WT__VGA_HSYNC_POL__SHIFT 10614 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h #define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x6
GENMO_WT__VGA_HSYNC_POL__SHIFT  846 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h #define GENMO_WT__VGA_HSYNC_POL__SHIFT                                                                        0x6
GENMO_WT__VGA_HSYNC_POL__SHIFT  257 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h #define GENMO_WT__VGA_HSYNC_POL__SHIFT                                                                        0x6