GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 9004 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT                                                                   0x5
GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 4734 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT                                                                   0x5
GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 4208 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT                                                                   0x5
GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 4114 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT                                                                   0x5
GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 4303 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x00000005
GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 14632 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5
GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 16560 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5
GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 17148 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5