GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT  284 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_sh_mask.h #define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12
GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT  280 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12
GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT  280 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12
GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT  282 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12
GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT  280 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12
GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT  308 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h #define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12