GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT  280 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_sh_mask.h #define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa
GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT  276 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa
GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT  276 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa
GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT  278 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa
GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT  276 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa
GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT  304 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h #define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa