GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK  279 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_sh_mask.h #define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00
GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK  275 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00
GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK  275 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00
GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK  277 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00
GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK  275 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00
GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK  303 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h #define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00