GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT  286 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_sh_mask.h #define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11
GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT  282 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11
GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT  282 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11
GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT  284 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11
GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT  282 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11
GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT  310 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h #define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11