GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 14806 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                         0xc
GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 9190 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                         0xc
GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 9036 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                         0xc