ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK  140 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_6_0_sh_mask.h #define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x00000700L
ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 4987 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_0_sh_mask.h #define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700
ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 5623 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h #define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700
ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 6103 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_sh_mask.h #define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700
ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 5981 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_sh_mask.h #define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700