ENABLE_MEM_PWR_CTRL 1185 drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_enum.h 	ENABLE_MEM_PWR_CTRL                              = 0x0,
ENABLE_MEM_PWR_CTRL 1055 drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_enum.h 	ENABLE_MEM_PWR_CTRL                              = 0x0,
ENABLE_MEM_PWR_CTRL 1760 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_enum.h 	ENABLE_MEM_PWR_CTRL                              = 0x0,
ENABLE_MEM_PWR_CTRL 5627 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_enum.h 	ENABLE_MEM_PWR_CTRL                              = 0x0,
ENABLE_MEM_PWR_CTRL 6265 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_enum.h 	ENABLE_MEM_PWR_CTRL                              = 0x0,
ENABLE_MEM_PWR_CTRL 6845 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_enum.h 	ENABLE_MEM_PWR_CTRL                              = 0x0,
ENABLE_MEM_PWR_CTRL 6795 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_enum.h 	ENABLE_MEM_PWR_CTRL                              = 0x0,
ENABLE_MEM_PWR_CTRL 1185 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_1_enum.h 	ENABLE_MEM_PWR_CTRL                              = 0x0,
ENABLE_MEM_PWR_CTRL 1055 drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_enum.h 	ENABLE_MEM_PWR_CTRL                              = 0x0,
ENABLE_MEM_PWR_CTRL 1451 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_enum.h 	ENABLE_MEM_PWR_CTRL                              = 0x0,
ENABLE_MEM_PWR_CTRL 1484 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_enum.h 	ENABLE_MEM_PWR_CTRL                              = 0x0,
ENABLE_MEM_PWR_CTRL 1233 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_enum.h 	ENABLE_MEM_PWR_CTRL                              = 0x0,
ENABLE_MEM_PWR_CTRL 1269 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_enum.h 	ENABLE_MEM_PWR_CTRL                              = 0x0,
ENABLE_MEM_PWR_CTRL 1055 drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_enum.h 	ENABLE_MEM_PWR_CTRL                              = 0x0,
ENABLE_MEM_PWR_CTRL 1198 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_enum.h 	ENABLE_MEM_PWR_CTRL                              = 0x0,
ENABLE_MEM_PWR_CTRL 1068 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_enum.h 	ENABLE_MEM_PWR_CTRL                              = 0x0,
ENABLE_MEM_PWR_CTRL 9539 drivers/gpu/drm/amd/include/navi10_enum.h ENABLE_MEM_PWR_CTRL                      = 0x00000000,
ENABLE_MEM_PWR_CTRL  204 drivers/gpu/drm/amd/include/vega10_enum.h ENABLE_MEM_PWR_CTRL                      = 0x00000000,
ENABLE_MEM_PWR_CTRL 1055 sound/soc/amd/include/acp_2_2_enum.h 	ENABLE_MEM_PWR_CTRL                              = 0x0,