DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 4114 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 0x1
DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 4222 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 0x1
DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 4686 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 0x1
DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 10646 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT                                                                  0x1
DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 6744 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h #define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 0x00000001
DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 4182 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h #define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 0x1
DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 41256 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h #define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT                                                                  0x1