DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO 1044 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_enum.h 	DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO     = 0x0,
DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO 5389 drivers/gpu/drm/amd/include/navi10_enum.h DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO  = 0x00000000,
DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO 11246 drivers/gpu/drm/amd/include/vega10_enum.h DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO  = 0x00000000,