DSCC5_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 53836 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h #define DSCC5_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
DSCC5_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 47276 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h #define DSCC5_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL