DSCC5_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 53775 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h #define DSCC5_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
DSCC5_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 47215 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h #define DSCC5_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L