DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 12695 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h #define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 15837 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h #define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 12769 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h #define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0