DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 12701 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h #define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 15843 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h #define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 12775 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h #define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1