DPM_TABLE_388__UvdLevel_7_MinVddcPhases_MASK 2155 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define DPM_TABLE_388__UvdLevel_7_MinVddcPhases_MASK 0xff00
DPM_TABLE_388__UvdLevel_7_MinVddcPhases_MASK 2157 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define DPM_TABLE_388__UvdLevel_7_MinVddcPhases_MASK 0xff00