DPM_TABLE_333__LinkLevel_5_PcieLaneCount__SHIFT 1954 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define DPM_TABLE_333__LinkLevel_5_PcieLaneCount__SHIFT 0x10
DPM_TABLE_333__LinkLevel_5_PcieLaneCount__SHIFT 1956 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define DPM_TABLE_333__LinkLevel_5_PcieLaneCount__SHIFT 0x10