DPM_TABLE_325__LinkLevel_3_PcieLaneCount_MASK 1925 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define DPM_TABLE_325__LinkLevel_3_PcieLaneCount_MASK 0xff0000
DPM_TABLE_325__LinkLevel_3_PcieLaneCount_MASK 1927 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define DPM_TABLE_325__LinkLevel_3_PcieLaneCount_MASK 0xff0000