DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 39159 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 32494 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h #define DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 41834 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h #define DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 37891 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h #define DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa