DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE_MASK 3593 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h #define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE_MASK                                                        0x00000030L
DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE_MASK 2362 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h #define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE_MASK                                                        0x00000030L
DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE_MASK 2094 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h #define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE_MASK                                                        0x00000030L