DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 2182 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 0x1
DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 2106 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 0x1
DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 2302 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 0x1
DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 3602 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT                                                        0x1
DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 6076 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h #define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 0x00000001
DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 2348 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h #define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 0x1