DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 3999 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h #define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000080L
DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 2773 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h #define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000080L
DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 2505 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h #define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000080L