DMCU_CTRL__RESET_UC__SHIFT 6744 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define DMCU_CTRL__RESET_UC__SHIFT 0x0
DMCU_CTRL__RESET_UC__SHIFT 6638 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define DMCU_CTRL__RESET_UC__SHIFT 0x0
DMCU_CTRL__RESET_UC__SHIFT 7718 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define DMCU_CTRL__RESET_UC__SHIFT 0x0
DMCU_CTRL__RESET_UC__SHIFT 4643 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define DMCU_CTRL__RESET_UC__SHIFT                                                                            0x0
DMCU_CTRL__RESET_UC__SHIFT 5662 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h #define DMCU_CTRL__RESET_UC__SHIFT 0x00000000
DMCU_CTRL__RESET_UC__SHIFT 7700 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h #define DMCU_CTRL__RESET_UC__SHIFT 0x0
DMCU_CTRL__RESET_UC__SHIFT 3613 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h #define DMCU_CTRL__RESET_UC__SHIFT                                                                            0x0
DMCU_CTRL__RESET_UC__SHIFT 2387 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h #define DMCU_CTRL__RESET_UC__SHIFT                                                                            0x0
DMCU_CTRL__RESET_UC__SHIFT 2119 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h #define DMCU_CTRL__RESET_UC__SHIFT                                                                            0x0