DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 12450 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_sh_mask.h #define DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK                                                        0x00000001L
DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 21183 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h #define DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK                                                        0x00000001L