DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 38936 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 32216 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h #define DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 41507 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h #define DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 37564 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h #define DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18