DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 43437 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT                                                                    0x1
DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 29172 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT                                                                    0x1
DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 30406 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT                                                                    0x1
DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 30679 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT                                                                    0x1
DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 18360 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x2
DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 20598 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x2
DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 21204 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x2