DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 43711 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT                                                                   0x1
DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 29427 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT                                                                   0x1
DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 30656 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT                                                                   0x1
DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 30896 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT                                                                   0x1
DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 18404 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x2
DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 20652 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x2
DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 21260 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x2