DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 43181 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT                                                                    0x1
DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 28942 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT                                                                    0x1
DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 30180 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT                                                                    0x1
DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 30469 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT                                                                    0x1
DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 18316 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x2
DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 20544 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x2
DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 21148 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x2