DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 2686 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0
DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 2700 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0
DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 2940 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0
DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 9001 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT                                                             0x0
DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 5226 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x00000000
DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 2888 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0
DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 39747 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT                                                             0x0
DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 48525 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT                                                             0x0
DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 43053 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT                                                             0x0