DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 2688 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8
DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 2702 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8
DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 2942 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8
DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 9002 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT                                                          0x8
DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 5224 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h #define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x00000008
DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 2890 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h #define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8
DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 39748 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h #define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT                                                          0x8
DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 48526 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h #define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT                                                          0x8
DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 43054 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h #define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT                                                          0x8