DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 3704 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10
DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 3792 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10
DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 4166 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10
DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 10150 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT                                                               0x10
DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 3394 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h #define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x00000010
DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 3800 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h #define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10
DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 40760 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h #define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT                                                               0x10
DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 49132 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h #define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT                                                               0x10
DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 43630 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h #define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT                                                               0x10