DCO_MEM_PWR_STATUS1__HDMILP1_MEM_PWR_STATE__SHIFT 15635 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define DCO_MEM_PWR_STATUS1__HDMILP1_MEM_PWR_STATE__SHIFT 0xc
DCO_MEM_PWR_STATUS1__HDMILP1_MEM_PWR_STATE__SHIFT 16317 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define DCO_MEM_PWR_STATUS1__HDMILP1_MEM_PWR_STATE__SHIFT 0xc
DCO_MEM_PWR_STATUS1__HDMILP1_MEM_PWR_STATE__SHIFT 8753 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define DCO_MEM_PWR_STATUS1__HDMILP1_MEM_PWR_STATE__SHIFT                                                     0xc