DCO_MEM_POWER_STATE__HDMI5_MEM_PWR_STATE__SHIFT 5058 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h #define DCO_MEM_POWER_STATE__HDMI5_MEM_PWR_STATE__SHIFT 0x0000001c
DCO_MEM_POWER_STATE__HDMI5_MEM_PWR_STATE__SHIFT 2928 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h #define DCO_MEM_POWER_STATE__HDMI5_MEM_PWR_STATE__SHIFT 0x1c