DCO_MEM_POWER_STATE__HDMI0_MEM_PWR_STATE__SHIFT 5048 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h #define DCO_MEM_POWER_STATE__HDMI0_MEM_PWR_STATE__SHIFT 0x00000012
DCO_MEM_POWER_STATE__HDMI0_MEM_PWR_STATE__SHIFT 2918 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h #define DCO_MEM_POWER_STATE__HDMI0_MEM_PWR_STATE__SHIFT 0x12