DCI_MEM_PWR_STATUS__MCIF_CWB1_MEM_PWR_STATE_MASK 2369 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define DCI_MEM_PWR_STATUS__MCIF_CWB1_MEM_PWR_STATE_MASK 0x300000
DCI_MEM_PWR_STATUS__MCIF_CWB1_MEM_PWR_STATE_MASK 2317 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define DCI_MEM_PWR_STATUS__MCIF_CWB1_MEM_PWR_STATE_MASK 0x300000