DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE__SHIFT 2400 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE__SHIFT 0x11
DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE__SHIFT 2348 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE__SHIFT 0x11
DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE__SHIFT 2542 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE__SHIFT 0x11
DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE__SHIFT 3766 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define DCI_MEM_PWR_STATUS2__DMIF4_DATA_MEM_PWR_STATE__SHIFT                                                  0x11